SCLAMP

Multi-vector signed clamp to minimum/maximum vector

This instruction clamps each signed element in the two or four destination vectors to between the signed minimum value in the corresponding element of the first source vector and the signed maximum value in the corresponding element of the second source vector and destructively places the clamped results in the corresponding elements of the two or four destination vectors.

This instruction is unpredicated.

Encoding: Two registers

Variants: FEAT_SME2 (ARMv9.3)

313029282726252423222120191817161514131211109876543210
1100000111100010
sizeZmZnZdU

SCLAMP { <Zd1>.<T>-<Zd2>.<T> }, <Zn>.<T>, <Zm>.<T>

Decoding algorithm

if !IsFeatureImplemented(FEAT_SME2) then EndOfDecode(Decode_UNDEF);
constant integer esize = 8 << UInt(size);
constant integer n = UInt(Zn);
constant integer m = UInt(Zm);
constant integer d = UInt(Zd:'0');
constant integer nreg = 2;

Encoding: Four registers

Variants: FEAT_SME2 (ARMv9.3)

313029282726252423222120191817161514131211109876543210
11000001111001100
sizeZmZnZdU

SCLAMP { <Zd1>.<T>-<Zd4>.<T> }, <Zn>.<T>, <Zm>.<T>

Decoding algorithm

if !IsFeatureImplemented(FEAT_SME2) then EndOfDecode(Decode_UNDEF);
constant integer esize = 8 << UInt(size);
constant integer n = UInt(Zn);
constant integer m = UInt(Zm);
constant integer d = UInt(Zd:'00');
constant integer nreg = 4;

Operation

CheckStreamingSVEEnabled();
constant integer VL = CurrentVL;
constant integer elements = VL DIV esize;
array [0..3] of bits(VL) results;

for r = 0 to nreg-1
    constant bits(VL) operand1 = Z[n, VL];
    constant bits(VL) operand2 = Z[m, VL];
    constant bits(VL) operand3 = Z[d+r, VL];
    for e = 0 to elements-1
        constant integer element1 = SInt(Elem[operand1, e, esize]);
        constant integer element2 = SInt(Elem[operand2, e, esize]);
        constant integer element3 = SInt(Elem[operand3, e, esize]);
        constant integer res = Min(Max(element1, element3), element2);
        Elem[results[r], e, esize] = res;

for r = 0 to nreg-1
    Z[d+r, VL] = results[r];

Explanations

<Zd1>: For the "Two registers" variant: is the name of the first scalable vector register of the destination multi-vector group, encoded as "Zd" times 2.
<Zd1>: For the "Four registers" variant: is the name of the first scalable vector register of the destination multi-vector group, encoded as "Zd" times 4.
<T>: <Zd2>: Is the name of the second scalable vector register of the destination multi-vector group, encoded as "Zd" times 2 plus 1.
<Zn>: Is the name of the first source scalable vector register, encoded in the "Zn" field.
<Zm>: Is the name of the second source scalable vector register, encoded in the "Zm" field.
<Zd4>: Is the name of the fourth scalable vector register of the destination multi-vector group, encoded as "Zd" times 4 plus 3.

Operational Notes

If PSTATE.DIT is 1: