SCVTF (scalar SIMD&FP)

Signed integer convert to floating-point (scalar SIMD&FP)

This instruction converts the signed integer value in the SIMD&FP source register to a floating-point value using the rounding mode that is specified by the FPCR, and writes the result to the SIMD&FP destination register.

This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exceptions and exception traps.

Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

Encoding: Integer

Variants: FEAT_FPRCVT (ARMv9.6)

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	0	0	1	1	1	1	0			1	1	1	1	0	0	0	0	0	0	0	0
sf		S						ftype			rmode		opcode									Rn					Rd

32-bit to half-precision (sf == 0 && ftype == 11)

SCVTF <Hd>, <Sn>

32-bit to double-precision (sf == 0 && ftype == 01)

SCVTF <Dd>, <Sn>

64-bit to half-precision (sf == 1 && ftype == 11)

SCVTF <Hd>, <Dn>

64-bit to single-precision (sf == 1 && ftype == 00)

SCVTF <Sd>, <Dn>

Decoding algorithm

if !IsFeatureImplemented(FEAT_FPRCVT) then EndOfDecode(Decode_UNDEF);
constant integer d = UInt(Rd);
constant integer n = UInt(Rn);

constant integer intsize = 32 << UInt(sf);
constant integer fltsize = 8 << UInt(ftype EOR '10');
constant FPRounding rounding = FPRoundingMode(FPCR);

Operation

CheckFPEnabled64();

bits(fltsize) fltval;
bits(intsize) intval;
constant boolean merge = IsMerging(FPCR);
bits(128) result = if merge then V[d, 128] else Zeros(128);

intval = V[n, intsize];
fltval = FixedToFP(intval, 0, FALSE, FPCR, rounding, fltsize);
Elem[result, 0, fltsize] = fltval;

V[d, 128] = result;

Explanations

<Hd>: Is the 16-bit name of the SIMD&FP destination register, encoded in the "Rd" field.
<Sn>: Is the 32-bit name of the SIMD&FP source register, encoded in the "Rn" field.
<Dd>: Is the 64-bit name of the SIMD&FP destination register, encoded in the "Rd" field.
<Dn>: Is the 64-bit name of the SIMD&FP source register, encoded in the "Rn" field.
<Sd>: Is the 32-bit name of the SIMD&FP destination register, encoded in the "Rd" field.