SHA1H

SHA1 fixed rotate

SHA1 fixed rotate.

Encoding: Advanced SIMD

Variants: FEAT_SHA1 (ARMv8.0)

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0	1	0	1	1	1	1	0	0	0	1	0	1	0	0	0	0	0	0	0	1	0
								size							opcode							Rn					Rd

SHA1H <Sd>, <Sn>

Decoding algorithm

if !IsFeatureImplemented(FEAT_SHA1) then EndOfDecode(Decode_UNDEF);
constant integer d = UInt(Rd);
constant integer n = UInt(Rn);

Operation

AArch64.CheckFPAdvSIMDEnabled();

constant bits(32) operand = V[n, 32];        // read element [0] only,  [1-3] zeroed
V[d, 32] = ROL(operand, 30);

Explanations

<Sd>: Is the 32-bit name of the SIMD&FP destination register, encoded in the "Rd" field.
<Sn>: Is the 32-bit name of the SIMD&FP source register, encoded in the "Rn" field.

Operational Notes

If PSTATE.DIT is 1:

• The execution time of this instruction is independent of:
  • The values of the data supplied in any of its registers.
  • The values of the NZCV flags.
• The response of this instruction to asynchronous exceptions does not vary based on:
  • The values of the data supplied in any of its registers.
  • The values of the NZCV flags.