SHA256H
SHA256 hash update (part 1)
SHA256 hash update (part 1).
Encoding: Advanced SIMD
Variants: FEAT_SHA256 (ARMv8.0)
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 1 | 0 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | | | | | | 0 | 1 | 0 | 0 | 0 | 0 | | | | | | | | | | |
| | | size | | Rm | | | P | | Rn | Rd |
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SHA256H <Qd>, <Qn>, <Vm>.4S
Decoding algorithm
if !IsFeatureImplemented(FEAT_SHA256) then EndOfDecode(Decode_UNDEF);
constant integer d = UInt(Rd);
constant integer n = UInt(Rn);
constant integer m = UInt(Rm);
Operation
AArch64.CheckFPAdvSIMDEnabled();
constant boolean part1 = TRUE;
V[d, 128] = SHA256hash(V[d, 128], V[n, 128], V[m, 128], part1);
Explanations
<Qd>:
Is the 128-bit name of the SIMD&FP source and destination, encoded in the "Rd" field.<Qn>:
Is the 128-bit name of the second SIMD&FP source register, encoded in the "Rn" field.<Vm>:
Is the name of the third SIMD&FP source register, encoded in the "Rm" field.Operational Notes
If PSTATE.DIT is 1:
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The execution time of this instruction is independent of:
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The values of the data supplied in any of its registers.
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The values of the NZCV flags.
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The response of this instruction to asynchronous exceptions does not vary based on:
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The values of the data supplied in any of its registers.
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The values of the NZCV flags.