SM3TT1B

SM3TT1B

This instruction takes three 128-bit vectors from three source SIMD&FP registers and a 2-bit immediate index value, and returns a 128-bit result in the destination SIMD&FP register. It performs a 32-bit majority function between the three 32-bit fields held in the upper three elements of the first source vector, and adds the resulting 32-bit value and the following three other 32-bit values:

  • The bottom 32-bit element of the first source vector, Vd, that was used for the 32-bit majority function.
  • The result of the exclusive-OR of the top 32-bit element of the second source vector, Vn, with a rotation left by 12 of the top 32-bit element of the first source vector.
  • A 32-bit element indexed out of the third source vector, Vm.

    • The result of this addition is returned as the top element of the result. The other elements of the result are taken from elements of the first source vector, with the element returned in bits<63:32> being rotated left by 9.

    Encoding: Advanced SIMD

    Variants: FEAT_SM3 (ARMv8.2)

    313029282726252423222120191817161514131211109876543210
    110011100101001
    Rmimm2opcodeRnRd

    SM3TT1B <Vd>.4S, <Vn>.4S, <Vm>.S[<imm2>]

    Decoding algorithm

    if !IsFeatureImplemented(FEAT_SM3) then EndOfDecode(Decode_UNDEF);
constant integer d = UInt(Rd);
constant integer n = UInt(Rn);
constant integer m = UInt(Rm);
constant integer i = UInt(imm2);

    Operation

    AArch64.CheckFPAdvSIMDEnabled();

constant bits(128) Vm = V[m, 128];
constant bits(128) Vn = V[n, 128];
constant bits(128) Vd = V[d, 128];

bits(32) WjPrime;
bits(128) result;
bits(32) TT1;
bits(32) SS2;

WjPrime = Elem[Vm, i, 32];
SS2 = Vn<127:96> EOR ROL(Vd<127:96>, 12);
TT1 = (Vd<127:96> AND Vd<63:32>) OR (Vd<127:96> AND Vd<95:64>) OR (Vd<63:32> AND Vd<95:64>);
TT1 = (TT1 + Vd<31:0> + SS2 + WjPrime)<31:0>;
result<31:0> = Vd<63:32>;
result<63:32> = ROL(Vd<95:64>, 9);
result<95:64> = Vd<127:96>;
result<127:96> = TT1;
V[d, 128] = result;

    Explanations

    <Vd>: Is the name of the SIMD&FP source and destination register, encoded in the "Rd" field.
    <Vn>: Is the name of the second SIMD&FP source register, encoded in the "Rn" field.
    <Vm>: Is the name of the third SIMD&FP source register, encoded in the "Rm" field.
    <imm2>: Is a 32-bit element indexed out of <Vm>, encoded in "imm2".

    Operational Notes

    If PSTATE.DIT is 1: