SQABS

Signed saturating absolute value

This instruction reads each vector element from the source SIMD&FP register, puts the absolute value of the result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values.

If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.

Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

Encoding: Scalar

Variants: FEAT_AdvSIMD (ARMv8.0)

313029282726252423222120191817161514131211109876543210
01011110100000011110
UsizeopcodeRnRd

SQABS <V><d>, <V><n>

Decoding algorithm

if !IsFeatureImplemented(FEAT_AdvSIMD) then EndOfDecode(Decode_UNDEF);
constant integer d = UInt(Rd);
constant integer n = UInt(Rn);
constant integer esize = 8 << UInt(size);
constant integer datasize = esize;
constant integer elements = 1;

Encoding: Vector

Variants: FEAT_AdvSIMD (ARMv8.0)

313029282726252423222120191817161514131211109876543210
0001110100000011110
QUsizeopcodeRnRd

SQABS <Vd>.<T>, <Vn>.<T>

Decoding algorithm

if !IsFeatureImplemented(FEAT_AdvSIMD) then EndOfDecode(Decode_UNDEF);
if size:Q == '110' then EndOfDecode(Decode_UNDEF);
constant integer d = UInt(Rd);
constant integer n = UInt(Rn);

constant integer esize = 8 << UInt(size);
constant integer datasize = 64 << UInt(Q);
constant integer elements = datasize DIV esize;

Operation

CheckFPAdvSIMDEnabled64();
constant bits(datasize) operand = V[n, datasize];
bits(datasize) result;
integer element;
boolean sat;

for e = 0 to elements-1
    element = SInt(Elem[operand, e, esize]);
    element = Abs(element);
    (Elem[result, e, esize], sat) = SignedSatQ(element, esize);
    if sat then FPSR.QC = '1';

V[d, datasize] = result;

Explanations

<V>: <d>: Is the number of the SIMD&FP destination register, encoded in the "Rd" field.
<n>: Is the number of the SIMD&FP source register, encoded in the "Rn" field.
<Vd>: Is the name of the SIMD&FP destination register, encoded in the "Rd" field.
<T>: <Vn>: Is the name of the SIMD&FP source register, encoded in the "Rn" field.