SQCVTN

Signed 32-bit integer saturating extract narrow and interleave to 16-bit integer

Saturate the signed integer value in each element of the group of two source vectors to half the original source element width, and place the two-way interleaved results in the half-width destination elements.

This instruction is unpredicated.

Encoding: SVE2

Variants: FEAT_SME2 || FEAT_SVE2p1 (FEAT_SME2 || FEAT_SVE2p1)

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0	1	0	0	0	1	0	1	0	0	1	1	0	0	0	1	0	1	0	0	0	0					0
									tszh		tszl									U		Zn					Zd

SQCVTN <Zd>.H, { <Zn1>.S-<Zn2>.S }

Decoding algorithm

if !IsFeatureImplemented(FEAT_SME2) && !IsFeatureImplemented(FEAT_SVE2p1) then
    EndOfDecode(Decode_UNDEF);
constant integer esize = 16;
constant integer n = UInt(Zn:'0');
constant integer d = UInt(Zd);

Operation

CheckSVEEnabled();
constant integer VL = CurrentVL;
constant integer elements = VL DIV (2 * esize);
bits(VL) result;

for e = 0 to elements-1
    for i = 0 to 1
        constant bits(VL) operand = Z[n+i, VL];
        constant integer element = SInt(Elem[operand, e, 2 * esize]);
        Elem[result, 2*e + i, esize] = SignedSat(element, esize);

Z[d, VL] = result;

Explanations

<Zd>: Is the name of the destination scalable vector register, encoded in the "Zd" field.
<Zn1>: Is the name of the first scalable vector register of the source multi-vector group, encoded as "Zn" times 2.
<Zn2>: Is the name of the second scalable vector register of the source multi-vector group, encoded as "Zn" times 2 plus 1.