SQDECH (scalar)

Signed saturating decrement scalar by multiple of 16-bit predicate constraint element count

Determines the number of active 16-bit elements implied by the named predicate constraint, multiplies that by an immediate in the range 1 to 16 inclusive, and then uses the result to decrement the scalar destination. The result is saturated to the source general-purpose register's signed integer range. A 32-bit saturated result is then sign-extended to 64 bits.

The named predicate constraint limits the number of active elements in a single predicate to:

  • A fixed number (VL1 to VL256)
  • The largest power of two (POW2)
  • The largest multiple of three or four (MUL3 or MUL4)
  • All available, implicitly a multiple of two (ALL).

    • Unspecified or out of range constraint encodings generate an empty predicate or zero element count rather than Undefined Instruction exception.

    Encoding: 32-bit

    Variants: FEAT_SVE || FEAT_SME (FEAT_SVE || FEAT_SME)

    313029282726252423222120191817161514131211109876543210
    000001000110111110
    sizesfimm4DUpatternRdn

    SQDECH <Xdn>, <Wdn>{, <pattern>{, MUL #<imm>}}

    Decoding algorithm

    if !IsFeatureImplemented(FEAT_SVE) && !IsFeatureImplemented(FEAT_SME) then
    EndOfDecode(Decode_UNDEF);
constant integer esize = 16;
constant integer dn = UInt(Rdn);
constant bits(5) pat = pattern;
constant integer imm = UInt(imm4) + 1;

constant boolean unsigned = FALSE;
constant integer ssize = 32;

    Encoding: 64-bit

    Variants: FEAT_SVE || FEAT_SME (FEAT_SVE || FEAT_SME)

    313029282726252423222120191817161514131211109876543210
    000001000111111110
    sizesfimm4DUpatternRdn

    SQDECH <Xdn>{, <pattern>{, MUL #<imm>}}

    Decoding algorithm

    if !IsFeatureImplemented(FEAT_SVE) && !IsFeatureImplemented(FEAT_SME) then
    EndOfDecode(Decode_UNDEF);
constant integer esize = 16;
constant integer dn = UInt(Rdn);
constant bits(5) pat = pattern;
constant integer imm = UInt(imm4) + 1;

constant boolean unsigned = FALSE;
constant integer ssize = 64;

    Operation

    CheckSVEEnabled();
constant integer count = DecodePredCount(pat, esize);
constant bits(ssize) operand1 = X[dn, ssize];
bits(ssize) result;
constant integer element1 = Int(operand1, unsigned);
(result, -) = SatQ(element1 - (count * imm), ssize, unsigned);
X[dn, 64] = Extend(result, 64, unsigned);

    Explanations

    <Xdn>: Is the 64-bit name of the source and destination general-purpose register, encoded in the "Rdn" field.
    <Wdn>: Is the 32-bit name of the source and destination general-purpose register, encoded in the "Rdn" field.
    <pattern>: <imm>: Is the immediate multiplier, in the range 1 to 16, defaulting to 1, encoded in the "imm4" field.