Signed saturating rounded shift right narrow (immediate)
This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, saturates each shifted result to a value that is half the original width, puts the final result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. All the values in this instruction are signed integer values. The destination vector elements are half as long as the source vector elements. The results are rounded. For truncated results, see SQSHRN.
The SQRSHRN instruction writes the vector to the lower half of the destination register and clears the upper half. The SQRSHRN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.
If saturation occurs, the cumulative saturation bit FPSR.QC is set.
Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Variants: FEAT_AdvSIMD (ARMv8.0)
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0 | 1 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | != 0000 | 1 | 0 | 0 | 1 | 1 | 1 | ||||||||||||||||
| U | immh | immb | op | Rn | Rd | ||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
SQRSHRN <Vb><d>, <Va><n>, #<shift>
if !IsFeatureImplemented(FEAT_AdvSIMD) then EndOfDecode(Decode_UNDEF); if immh == '0000' then EndOfDecode(Decode_UNDEF); if immh<3> == '1' then EndOfDecode(Decode_UNDEF); constant integer d = UInt(Rd); constant integer n = UInt(Rn); constant integer esize = 8 << HighestSetBitNZ(immh<2:0>); constant integer datasize = esize; constant integer elements = 1; constant integer part = 0; constant integer shift = (2 * esize) - UInt(immh:immb); constant boolean round = TRUE; constant boolean unsigned = FALSE;
Variants: FEAT_AdvSIMD (ARMv8.0)
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0 | 0 | 0 | 1 | 1 | 1 | 1 | 0 | != 0000 | 1 | 0 | 0 | 1 | 1 | 1 | |||||||||||||||||
| Q | U | immh | immb | op | Rn | Rd | |||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
SQRSHRN{2} <Vd>.<Tb>, <Vn>.<Ta>, #<shift>
if !IsFeatureImplemented(FEAT_AdvSIMD) then EndOfDecode(Decode_UNDEF); if immh == '0000' then SEE(asimdimm); if immh<3> == '1' then EndOfDecode(Decode_UNDEF); constant integer d = UInt(Rd); constant integer n = UInt(Rn); constant integer esize = 8 << HighestSetBitNZ(immh<2:0>); constant integer datasize = 64; constant integer part = UInt(Q); constant integer elements = datasize DIV esize; constant integer shift = (2 * esize) - UInt(immh:immb); constant boolean round = TRUE; constant boolean unsigned = FALSE;
CheckFPAdvSIMDEnabled64(); constant bits(datasize*2) operand = V[n, datasize*2]; bits(datasize) result; integer element; boolean sat; for e = 0 to elements-1 element = RShr(Int(Elem[operand, e, 2*esize], unsigned), shift, round); (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned); if sat then FPSR.QC = '1'; Vpart[d, part, datasize] = result;