SQXTNT

Signed saturating extract narrow (top)

Saturate the signed integer value in each source element to half the original source element width, and place the results in the odd-numbered half-width destination elements, leaving the even-numbered elements unchanged.

Encoding: SVE2

Variants: FEAT_SVE2 || FEAT_SME (FEAT_SVE2 || FEAT_SME)

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0	1	0	0	0	1	0	1	0		1			0	0	0	0	1	0	0	0	1
									tszh		tszl									U	T	Zn					Zd

SQXTNT <Zd>.<T>, <Zn>.<Tb>

Decoding algorithm

if !IsFeatureImplemented(FEAT_SVE2) && !IsFeatureImplemented(FEAT_SME) then
    EndOfDecode(Decode_UNDEF);
constant bits(3) tsize = tszh:tszl;
if !(tsize IN {'001', '010', '100'}) then EndOfDecode(Decode_UNDEF);
constant integer esize = 16 << HighestSetBitNZ(tsize);
constant integer n = UInt(Zn);
constant integer d = UInt(Zd);

Operation

CheckSVEEnabled();
constant integer VL = CurrentVL;
constant integer elements = VL DIV esize;
constant bits(VL) operand1 = Z[n, VL];
bits(VL) result = Z[d, VL];
constant integer halfesize = esize DIV 2;

for e = 0 to elements-1
    constant integer element1 = SInt(Elem[operand1, e, esize]);
    constant bits(halfesize) res = SignedSat(element1, halfesize);
    Elem[result, 2*e + 1, halfesize] = res;

Z[d, VL] = result;

Explanations

<Zd>: Is the name of the destination scalable vector register, encoded in the "Zd" field.
<T>: <Zn>: Is the name of the source scalable vector register, encoded in the "Zn" field.
<Tb>: