STADD, STADDL

Atomic add on word or doubleword in memory, without return

This instruction atomically loads a 32-bit word or 64-bit doubleword from memory, adds the value held in a register to it, and stores the result back to memory.

  • STADD does not have release semantics.
  • STADDL stores to memory with release semantics, as described in Load-Acquire, Store-Release.

    • For information about addressing modes, see Load/Store addressing modes.

    Encoding: Integer

    Variants: FEAT_LSE (ARMv8.1)

    313029282726252423222120191817161514131211109876543210
    1x1110000100000011111
    sizeVRARRso3opcRnRt

    32-bit no memory ordering (size == 10 && R == 0)

    STADD <Ws>, [<Xn|SP>]

    Equivalent to: LDADD <Ws>, WZR, [<Xn|SP>]

    32-bit release (size == 10 && R == 1)

    STADDL <Ws>, [<Xn|SP>]

    Equivalent to: LDADDL <Ws>, WZR, [<Xn|SP>]

    64-bit no memory ordering (size == 11 && R == 0)

    STADD <Xs>, [<Xn|SP>]

    Equivalent to: LDADD <Xs>, XZR, [<Xn|SP>]

    64-bit release (size == 11 && R == 1)

    STADDL <Xs>, [<Xn|SP>]

    Equivalent to: LDADDL <Xs>, XZR, [<Xn|SP>]

    Explanations

    <Ws>: Is the 32-bit name of the general-purpose register holding the data value to be operated on with the contents of the memory location, encoded in the "Rs" field.
    <Xn|SP>: Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
    <Xs>: Is the 64-bit name of the general-purpose register holding the data value to be operated on with the contents of the memory location, encoded in the "Rs" field.

    Operational Notes

    If PSTATE.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored.