STR (immediate, SIMD&FP)

Store SIMD&FP register (immediate offset)

This instruction stores a single SIMD&FP register to memory. The address that is used for the store is calculated from a base register value and an immediate offset.

Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

Encoding: Post-index

Variants: FEAT_FP (ARMv8.0)

313029282726252423222120191817161514131211109876543210
111100x0001
sizeVRopcimm9RnRt

8-bit (size == 00 && opc == 00)

STR <Bt>, [<Xn|SP>], #<simm>

16-bit (size == 01 && opc == 00)

STR <Ht>, [<Xn|SP>], #<simm>

32-bit (size == 10 && opc == 00)

STR <St>, [<Xn|SP>], #<simm>

64-bit (size == 11 && opc == 00)

STR <Dt>, [<Xn|SP>], #<simm>

128-bit (size == 00 && opc == 10)

STR <Qt>, [<Xn|SP>], #<simm>

Decoding algorithm

if !IsFeatureImplemented(FEAT_FP) then EndOfDecode(Decode_UNDEF);
if opc<1> == '1' && size != '00' then EndOfDecode(Decode_UNDEF);
constant integer scale = if opc<1> == '1' then 4 else UInt(size);
constant boolean wback = TRUE;
constant boolean postindex = TRUE;
constant bits(64) offset = SignExtend(imm9, 64);

Encoding: Pre-index

Variants: FEAT_FP (ARMv8.0)

313029282726252423222120191817161514131211109876543210
111100x0011
sizeVRopcimm9RnRt

8-bit (size == 00 && opc == 00)

STR <Bt>, [<Xn|SP>, #<simm>]!

16-bit (size == 01 && opc == 00)

STR <Ht>, [<Xn|SP>, #<simm>]!

32-bit (size == 10 && opc == 00)

STR <St>, [<Xn|SP>, #<simm>]!

64-bit (size == 11 && opc == 00)

STR <Dt>, [<Xn|SP>, #<simm>]!

128-bit (size == 00 && opc == 10)

STR <Qt>, [<Xn|SP>, #<simm>]!

Decoding algorithm

if !IsFeatureImplemented(FEAT_FP) then EndOfDecode(Decode_UNDEF);
if opc<1> == '1' && size != '00' then EndOfDecode(Decode_UNDEF);
constant integer scale = if opc<1> == '1' then 4 else UInt(size);
constant boolean wback = TRUE;
constant boolean postindex = FALSE;
constant bits(64) offset = SignExtend(imm9, 64);

Encoding: Unsigned offset

Variants: FEAT_FP (ARMv8.0)

313029282726252423222120191817161514131211109876543210
111101x0
sizeVRopcimm12RnRt

8-bit (size == 00 && opc == 00)

STR <Bt>, [<Xn|SP>{, #<pimm>}]

16-bit (size == 01 && opc == 00)

STR <Ht>, [<Xn|SP>{, #<pimm>}]

32-bit (size == 10 && opc == 00)

STR <St>, [<Xn|SP>{, #<pimm>}]

64-bit (size == 11 && opc == 00)

STR <Dt>, [<Xn|SP>{, #<pimm>}]

128-bit (size == 00 && opc == 10)

STR <Qt>, [<Xn|SP>{, #<pimm>}]

Decoding algorithm

if !IsFeatureImplemented(FEAT_FP) then EndOfDecode(Decode_UNDEF);
if opc<1> == '1' && size != '00' then EndOfDecode(Decode_UNDEF);
constant integer scale = if opc<1> == '1' then 4 else UInt(size);
constant boolean wback = FALSE;
constant boolean postindex = FALSE;
constant bits(64) offset = LSL(ZeroExtend(imm12, 64), scale);

Operation

constant integer t = UInt(Rt);
constant integer n = UInt(Rn);
constant integer datasize = 8 << scale;
constant boolean nontemporal = FALSE;
constant boolean tagchecked = wback || n != 31;
CheckFPEnabled64();
bits(64) address;

constant boolean privileged = PSTATE.EL != EL0;
constant AccessDescriptor accdesc = CreateAccDescASIMD(MemOp_STORE, nontemporal, tagchecked,
                                                       privileged);

if n == 31 then
    CheckSPAlignment();
    address = SP[64];
else
    address = X[n, 64];

if !postindex then
    address = AddressAdd(address, offset, accdesc);

Mem[address, datasize DIV 8, accdesc] = V[t, datasize];

if wback then
    if postindex then
        address = AddressAdd(address, offset, accdesc);
    if n == 31 then
        SP[64] = address;
    else
        X[n, 64] = address;

Explanations

<Bt>: Is the 8-bit name of the SIMD&FP register to be transferred, encoded in the "Rt" field.
<Xn|SP>: Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
<simm>: Is the signed immediate byte offset, in the range -256 to 255, encoded in the "imm9" field.
<Ht>: Is the 16-bit name of the SIMD&FP register to be transferred, encoded in the "Rt" field.
<St>: Is the 32-bit name of the SIMD&FP register to be transferred, encoded in the "Rt" field.
<Dt>: Is the 64-bit name of the SIMD&FP register to be transferred, encoded in the "Rt" field.
<Qt>: Is the 128-bit name of the SIMD&FP register to be transferred, encoded in the "Rt" field.
<pimm>: For the "8-bit" variant: is the optional positive immediate byte offset, in the range 0 to 4095, defaulting to 0 and encoded in the "imm12" field.
<pimm>: For the "16-bit" variant: is the optional positive immediate byte offset, a multiple of 2 in the range 0 to 8190, defaulting to 0 and encoded in the "imm12" field as <pimm>/2.
<pimm>: For the "32-bit" variant: is the optional positive immediate byte offset, a multiple of 4 in the range 0 to 16380, defaulting to 0 and encoded in the "imm12" field as <pimm>/4.
<pimm>: For the "64-bit" variant: is the optional positive immediate byte offset, a multiple of 8 in the range 0 to 32760, defaulting to 0 and encoded in the "imm12" field as <pimm>/8.
<pimm>: For the "128-bit" variant: is the optional positive immediate byte offset, a multiple of 16 in the range 0 to 65520, defaulting to 0 and encoded in the "imm12" field as <pimm>/16.

Operational Notes

If PSTATE.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored.