STTCLR, STTCLRL

Atomic bit clear unprivileged, without return

This instruction atomically loads a 32-bit word or 64-bit doubleword from memory, performs a bitwise AND with the complement of the value held in a register on it, and stores the result back to memory.

  • STTCLR does not have release semantics.
  • STTCLRL stores to memory with release semantics, as described in Load-Acquire, Store-Release.

    • For information about addressing modes, see Load/Store addressing modes.

    Encoding: Integer

    Variants: FEAT_LSUI (ARMv9.6)

    313029282726252423222120191817161514131211109876543210
    00110010100010111111
    szARRso3opcRnRt

    32-bit no memory ordering (sz == 0 && R == 0)

    STTCLR <Ws>, [<Xn|SP>]

    Equivalent to: LDTCLR <Ws>, WZR, [<Xn|SP>]

    32-bit release (sz == 0 && R == 1)

    STTCLRL <Ws>, [<Xn|SP>]

    Equivalent to: LDTCLRL <Ws>, WZR, [<Xn|SP>]

    64-bit no memory ordering (sz == 1 && R == 0)

    STTCLR <Xs>, [<Xn|SP>]

    Equivalent to: LDTCLR <Xs>, XZR, [<Xn|SP>]

    64-bit release (sz == 1 && R == 1)

    STTCLRL <Xs>, [<Xn|SP>]

    Equivalent to: LDTCLRL <Xs>, XZR, [<Xn|SP>]

    Explanations

    <Ws>: Is the 32-bit name of the general-purpose register holding the data value to be operated on with the contents of the memory location, encoded in the "Rs" field.
    <Xn|SP>: Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
    <Xs>: Is the 64-bit name of the general-purpose register holding the data value to be operated on with the contents of the memory location, encoded in the "Rs" field.

    Operational Notes

    If PSTATE.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored.