STTP (SIMD&FP)

Store unprivileged pair of SIMD&FP registers

This instruction stores a pair of SIMD&FP registers to memory. The address used for the store is calculated from a base register value and an immediate offset.

Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

Explicit Memory effects produced by the instruction behave as if the instruction was executed at EL0 if the Effective value of PSTATE.UAO is 0 and either:

  • The instruction is executed at EL1.
  • The instruction is executed at EL2 when the Effective value of HCR_EL2.{E2H, TGE} is {1, 1}.

    • Otherwise, the Explicit Memory effects operate with the restrictions determined by the Exception level at which the instruction is executed.

    Encoding: Post-index

    Variants: FEAT_FP && FEAT_LSUI (FEAT_FP && FEAT_LSUI)

    313029282726252423222120191817161514131211109876543210
    1110110010
    opcVRLimm7Rt2RnRt

    STTP <Qt1>, <Qt2>, [<Xn|SP>], #<imm>

    Decoding algorithm

    if !IsFeatureImplemented(FEAT_FP) || !IsFeatureImplemented(FEAT_LSUI) then
    EndOfDecode(Decode_UNDEF);

constant boolean wback = TRUE;
constant boolean postindex = TRUE;

    Encoding: Pre-index

    Variants: FEAT_FP && FEAT_LSUI (FEAT_FP && FEAT_LSUI)

    313029282726252423222120191817161514131211109876543210
    1110110110
    opcVRLimm7Rt2RnRt

    STTP <Qt1>, <Qt2>, [<Xn|SP>, #<imm>]!

    Decoding algorithm

    if !IsFeatureImplemented(FEAT_FP) || !IsFeatureImplemented(FEAT_LSUI) then
    EndOfDecode(Decode_UNDEF);

constant boolean wback = TRUE;
constant boolean postindex = FALSE;

    Encoding: Signed offset

    Variants: FEAT_FP && FEAT_LSUI (FEAT_FP && FEAT_LSUI)

    313029282726252423222120191817161514131211109876543210
    1110110100
    opcVRLimm7Rt2RnRt

    STTP <Qt1>, <Qt2>, [<Xn|SP>{, #<imm>}]

    Decoding algorithm

    if !IsFeatureImplemented(FEAT_FP) || !IsFeatureImplemented(FEAT_LSUI) then
    EndOfDecode(Decode_UNDEF);

constant boolean wback = FALSE;
constant boolean postindex = FALSE;

    Operation

    constant integer t = UInt(Rt);
constant integer t2 = UInt(Rt2);
constant integer n = UInt(Rn);
constant boolean nontemporal = FALSE;
constant integer datasize = 128;
constant bits(64) offset = LSL(SignExtend(imm7, 64), 4);
constant boolean tagchecked = wback || n != 31;

    CheckFPEnabled64();
bits(64) address;
constant integer dbytes = datasize DIV 8;

constant boolean privileged = AArch64.IsUnprivAccessPriv();
constant boolean ispair = IsFeatureImplemented(FEAT_LS64WB) && datasize == 128;
constant AccessDescriptor accdesc = CreateAccDescASIMD(MemOp_STORE, nontemporal,
                                                       tagchecked, privileged, ispair);

if n == 31 then
    CheckSPAlignment();
    address = SP[64];
else
    address = X[n, 64];

if !postindex then
    address = AddressAdd(address, offset, accdesc);

if accdesc.ispair then
    bits(2*datasize) full_data;
    if BigEndian(accdesc.acctype) then
        full_data = V[t, datasize] : V[t2, datasize];
    else
        full_data = V[t2, datasize] : V[t, datasize];

    Mem[address, 2*dbytes, accdesc] = full_data;
else
    constant bits(64) address2 = AddressIncrement(address, dbytes, accdesc);
    Mem[address , dbytes, accdesc] = V[t , datasize];
    Mem[address2, dbytes, accdesc] = V[t2, datasize];

if wback then
    if postindex then
        address = AddressAdd(address, offset, accdesc);
    if n == 31 then
        SP[64] = address;
    else
        X[n, 64] = address;

    Explanations

    <Qt1>: Is the 128-bit name of the first SIMD&FP register to be transferred, encoded in the "Rt" field.
    <Qt2>: Is the 128-bit name of the second SIMD&FP register to be transferred, encoded in the "Rt2" field.
    <Xn|SP>: Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
    <imm>: For the "Post-index" and "Pre-index" variants: is the signed immediate byte offset, a multiple of 16 in the range -1024 to 1008, encoded in the "imm7" field as <imm>/16.
    <imm>: For the "Signed offset" variant: is the optional signed immediate byte offset, a multiple of 16 in the range -1024 to 1008, defaulting to 0 and encoded in the "imm7" field as <imm>/16.

    Operational Notes

    If PSTATE.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored.