STTSET, STTSETL

Atomic bit set unprivileged, without return

This instruction atomically loads a 32-bit word or 64-bit doubleword from memory, performs a bitwise OR with the value held in a register on it, and stores the result back to memory.

STTSET does not have release semantics.

STTSETL stores to memory with release semantics, as described in Load-Acquire, Store-Release.

For information about addressing modes, see Load/Store addressing modes.

Encoding: Integer

Variants: FEAT_LSUI (ARMv9.6)

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0		0	1	1	0	0	1	0		1						0	0	1	1	0	1						1	1	1	1	1
	sz							A	R		Rs					o3	opc					Rn					Rt

32-bit no memory ordering (sz == 0 && R == 0)

STTSET <Ws>, [<Xn|SP>]

Equivalent to: LDTSET <Ws>, WZR, [<Xn|SP>]

32-bit release (sz == 0 && R == 1)

STTSETL <Ws>, [<Xn|SP>]

Equivalent to: LDTSETL <Ws>, WZR, [<Xn|SP>]

64-bit no memory ordering (sz == 1 && R == 0)

STTSET <Xs>, [<Xn|SP>]

Equivalent to: LDTSET <Xs>, XZR, [<Xn|SP>]

64-bit release (sz == 1 && R == 1)

STTSETL <Xs>, [<Xn|SP>]

Equivalent to: LDTSETL <Xs>, XZR, [<Xn|SP>]

Explanations

<Ws>: Is the 32-bit name of the general-purpose register holding the data value to be operated on with the contents of the memory location, encoded in the "Rs" field.
<Xn|SP>: Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
<Xs>: Is the 64-bit name of the general-purpose register holding the data value to be operated on with the contents of the memory location, encoded in the "Rs" field.

Operational Notes

If PSTATE.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored.