SXTH

Sign extend halfword

This instruction extracts a 16-bit value, sign-extends it to the size of the register, and writes the result to the destination register.

Encoding: With sign replication to left and zeros to right

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	0	0	1	0	0	1	1	0		0	0	0	0	0	0	0	0	1	1	1	1
sf	opc								N	immr						imms						Rn					Rd

32-bit (sf == 0 && N == 0)

SXTH <Wd>, <Wn>

Equivalent to: SBFM <Wd>, <Wn>, #0, #15

64-bit (sf == 1 && N == 1)

SXTH <Xd>, <Wn>

Equivalent to: SBFM <Xd>, <Xn>, #0, #15

Explanations

<Wd>: Is the 32-bit name of the general-purpose destination register, encoded in the "Rd" field.
<Wn>: Is the 32-bit name of the general-purpose source register, encoded in the "Rn" field.
<Xd>: Is the 64-bit name of the general-purpose destination register, encoded in the "Rd" field.

Operational Notes

If PSTATE.DIT is 1:

• The execution time of this instruction is independent of:
  • The values of the data supplied in any of its registers.
  • The values of the NZCV flags.
• The response of this instruction to asynchronous exceptions does not vary based on:
  • The values of the data supplied in any of its registers.
  • The values of the NZCV flags.