SYSP

128-bit system instruction

128-bit system instruction.

Encoding: System

Variants: FEAT_SYSINSTR128 (ARMv9.4)

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
1	1	0	1	0	1	0	1	0	1	0	0	1
										L			op1			CRn				CRm				op2			Rt

SYSP #<op1>, <Cn>, <Cm>, #<op2>{, <Xt1>, <Xt2>}

Decoding algorithm

if !IsFeatureImplemented(FEAT_SYSINSTR128) then EndOfDecode(Decode_UNDEF);
if Rt<0> == '1' && Rt != '11111' then EndOfDecode(Decode_UNDEF);

constant integer t       = UInt(Rt);
constant integer t2      = if t == 31 then 31 else t + 1;
constant bits(1) sys_L   = L;
constant bits(2) sys_op0 = '01';
constant bits(3) sys_op1 = op1;
constant bits(3) sys_op2 = op2;
constant bits(4) sys_crn = CRn;
constant bits(4) sys_crm = CRm;

Operation

AArch64.CheckSystemAccess(sys_op0, sys_op1, sys_crn, sys_crm, sys_op2, t, sys_L);
AArch64.SysInstr128(sys_op0, sys_op1, sys_crn, sys_crm, sys_op2, t, t2);

Explanations

<op1>: Is a 3-bit unsigned immediate, in the range 0 to 6, encoded in the "op1" field.
<Cn>: Is a name 'Cn', with 'n' in the range 8 to 9, encoded in the "CRn" field.
<Cm>: Is a name 'Cm', with 'm' in the range 0 to 7, encoded in the "CRm" field.
<op2>: Is a 3-bit unsigned immediate, in the range 0 to 7, encoded in the "op2" field.
<Xt1>: Is the 64-bit name of the first optional general-purpose source register, defaulting to '11111', encoded in the "Rt" field.
<Xt2>: Is the 64-bit name of the second optional general-purpose source register, defaulting to '11111', encoded as "Rt" +1. Defaults to '11111' if "Rt" = '11111'.