TST (shifted register)

Test (shifted register)

This instruction performs a bitwise AND operation on a register value and an optionally-shifted register value. It updates the condition flags based on the result, and discards the result.

Encoding: Setting the condition flags

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	1	1	0	1	0	1	0			0																	1	1	1	1	1
sf	opc							shift		N	Rm					imm6						Rn					Rd

32-bit (sf == 0)

TST <Wn>, <Wm>{, <shift> #<amount>}

Equivalent to: ANDS WZR, <Wn>, <Wm>{, <shift> #<amount>}

64-bit (sf == 1)

TST <Xn>, <Xm>{, <shift> #<amount>}

Equivalent to: ANDS XZR, <Xn>, <Xm>{, <shift> #<amount>}

Explanations

<Wn>: Is the 32-bit name of the first general-purpose source register, encoded in the "Rn" field.
<Wm>: Is the 32-bit name of the second general-purpose source register, encoded in the "Rm" field.
<shift>: <amount>: For the "32-bit" variant: is the shift amount, in the range 0 to 31, defaulting to 0 and encoded in the "imm6" field.
<amount>: For the "64-bit" variant: is the shift amount, in the range 0 to 63, defaulting to 0 and encoded in the "imm6" field.
<Xn>: Is the 64-bit name of the first general-purpose source register, encoded in the "Rn" field.
<Xm>: Is the 64-bit name of the second general-purpose source register, encoded in the "Rm" field.

Operational Notes

If PSTATE.DIT is 1:

• The execution time of this instruction is independent of:
  • The values of the data supplied in any of its registers.
  • The values of the NZCV flags.
• The response of this instruction to asynchronous exceptions does not vary based on:
  • The values of the data supplied in any of its registers.
  • The values of the NZCV flags.