UMULH (unpredicated)

Unsigned multiply returning high half (unpredicated)

Widening multiply unsigned integer values of all elements of the first source vector by corresponding elements of the second source vector and place the high half of the result in the corresponding elements of the destination vector. This instruction is unpredicated.

Encoding: SVE2

Variants: FEAT_SVE2 || FEAT_SME (FEAT_SVE2 || FEAT_SME)

313029282726252423222120191817161514131211109876543210
000001001011011
sizeZmUZnZd

UMULH <Zd>.<T>, <Zn>.<T>, <Zm>.<T>

Decoding algorithm

if !IsFeatureImplemented(FEAT_SVE2) && !IsFeatureImplemented(FEAT_SME) then
    EndOfDecode(Decode_UNDEF);
constant integer esize = 8 << UInt(size);
constant integer n = UInt(Zn);
constant integer m = UInt(Zm);
constant integer d = UInt(Zd);
constant boolean unsigned = TRUE;

Operation

CheckSVEEnabled();
constant integer VL = CurrentVL;
constant integer elements = VL DIV esize;
constant bits(VL) operand1 = Z[n, VL];
constant bits(VL) operand2 = Z[m, VL];
bits(VL) result;

for e = 0 to elements-1
    constant integer element1 = Int(Elem[operand1, e, esize], unsigned);
    constant integer element2 = Int(Elem[operand2, e, esize], unsigned);
    constant integer product = (element1 * element2) >> esize;
    Elem[result, e, esize] = product;

Z[d, VL] = result;

Explanations

<Zd>: Is the name of the destination scalable vector register, encoded in the "Zd" field.
<T>: <Zn>: Is the name of the first source scalable vector register, encoded in the "Zn" field.
<Zm>: Is the name of the second source scalable vector register, encoded in the "Zm" field.

Operational Notes

If PSTATE.DIT is 1: