ZERO (double-vector)

Zero ZA double-vector groups

This instruction zeroes one, two, or four ZA double-vector groups.

The double-vector group within all of, each half of, or each quarter of the ZA array is selected by the sum of the vector select register and offset range, modulo all, half, or quarter the number of ZA array vectors.

The vector group symbol, VGx2 or VGx4, indicates that the ZA operand consists of two or four ZA double-vector groups respectively.

Encoding: One ZA double-vector

Variants: FEAT_SME2p1 (ARMv9.4)

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
1	1	0	0	0	0	0	0	0	0	0	0	1	1	0	0	1			0	0	0	0	0	0	0	0	0	0
														opc			Rv												off3

ZERO ZA.D[<Wv>, <offs1>:<offs2>]

Decoding algorithm

if !IsFeatureImplemented(FEAT_SME2p1) then EndOfDecode(Decode_UNDEF);
constant integer v = UInt('010':Rv);
constant integer offset = UInt(off3:'0');
constant integer ngrp = 1;
constant integer nvec = 2;

Encoding: Two ZA double-vectors

Variants: FEAT_SME2p1 (ARMv9.4)

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
1	1	0	0	0	0	0	0	0	0	0	0	1	1	0	1	0			0	0	0	0	0	0	0	0	0	0	0
														opc			Rv													off2

ZERO ZA.D[<Wv>, <offs1>:<offs2>, VGx2]

Decoding algorithm

if !IsFeatureImplemented(FEAT_SME2p1) then EndOfDecode(Decode_UNDEF);
constant integer v = UInt('010':Rv);
constant integer offset = UInt(off2:'0');
constant integer ngrp = 2;
constant integer nvec = 2;

Encoding: Four ZA double-vectors

Variants: FEAT_SME2p1 (ARMv9.4)

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
1	1	0	0	0	0	0	0	0	0	0	0	1	1	0	1	1			0	0	0	0	0	0	0	0	0	0	0
														opc			Rv													off2

ZERO ZA.D[<Wv>, <offs1>:<offs2>, VGx4]

Decoding algorithm

if !IsFeatureImplemented(FEAT_SME2p1) then EndOfDecode(Decode_UNDEF);
constant integer v = UInt('010':Rv);
constant integer offset = UInt(off2:'0');
constant integer ngrp = 4;
constant integer nvec = 2;

Operation

CheckStreamingSVEAndZAEnabled();
constant integer VL = CurrentVL;
constant integer vectors = VL DIV 8;
constant integer vstride = vectors DIV ngrp;
constant bits(32) vbase = X[v, 32];
integer vec = (UInt(vbase) + offset) MOD vstride;
vec = vec - (vec MOD nvec);
for r = 0 to ngrp-1
    for i = 0 to nvec-1
        ZAvector[vec + i, VL] = Zeros(VL);
    vec = vec + vstride;

Explanations

<Wv>: Is the 32-bit name of the vector select register W8-W11, encoded in the "Rv" field.
<offs1>: For the "One ZA double-vector" variant: is the first vector select offset, encoded as "off3" field times 2.
<offs1>: For the "Four ZA double-vectors" and "Two ZA double-vectors" variants: is the first vector select offset, encoded as "off2" field times 2.
<offs2>: For the "One ZA double-vector" variant: is the second vector select offset, encoded as "off3" field times 2 plus 1.
<offs2>: For the "Four ZA double-vectors" and "Two ZA double-vectors" variants: is the second vector select offset, encoded as "off2" field times 2 plus 1.

Operational Notes

If PSTATE.DIT is 1:

• The execution time of this instruction is independent of:
  • The values of the data supplied in any of its registers.
  • The values of the NZCV flags.
• The response of this instruction to asynchronous exceptions does not vary based on:
  • The values of the data supplied in any of its registers.
  • The values of the NZCV flags.