Bitwise OR NOT (shifted register) performs a bitwise (inclusive) OR of a register value and the complement of an optionally-shifted register value, and writes the result to the destination register.
This instruction is used by the alias MVN.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
sf | 0 | 1 | 0 | 1 | 0 | 1 | 0 | shift | 1 | Rm | imm6 | Rn | Rd | ||||||||||||||||||
opc | N |
integer d = UInt(Rd); integer n = UInt(Rn); integer m = UInt(Rm); constant integer datasize = 32 << UInt(sf); if sf == '0' && imm6<5> == '1' then UNDEFINED; ShiftType shift_type = DecodeShift(shift); integer shift_amount = UInt(imm6);
<Wd> | Is the 32-bit name of the general-purpose destination register, encoded in the "Rd" field. |
<Wn> | Is the 32-bit name of the first general-purpose source register, encoded in the "Rn" field. |
<Wm> | Is the 32-bit name of the second general-purpose source register, encoded in the "Rm" field. |
<Xd> | Is the 64-bit name of the general-purpose destination register, encoded in the "Rd" field. |
<Xn> | Is the 64-bit name of the first general-purpose source register, encoded in the "Rn" field. |
<Xm> | Is the 64-bit name of the second general-purpose source register, encoded in the "Rm" field. |
<shift> | Is the optional shift to be applied to the final source, defaulting to LSL and encoded in
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Alias | Is preferred when |
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MVN | Rn == '11111' |
bits(datasize) operand1 = X[n, datasize]; bits(datasize) operand2 = ShiftReg(m, shift_type, shift_amount, datasize); bits(datasize) result; operand2 = NOT(operand2); result = operand1 OR operand2; X[d, datasize] = result;
If PSTATE.DIT is 1: