STCLRH, STCLRLH

Atomic bit clear on halfword in memory, without return

This instruction atomically loads a 16-bit halfword from memory, performs a bitwise AND with the complement of the value held in a register on it, and stores the result back to memory.

STCLRH does not have release semantics.

STCLRLH stores to memory with release semantics, as described in Load-Acquire, Store-Release.

For information about addressing modes, see Load/Store addressing modes.

Encoding: Integer

Variants: FEAT_LSE (ARMv8.1)

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0	1	1	1	1	0	0	0	0		1						0	0	0	1	0	0						1	1	1	1	1
size					VR			A	R		Rs					o3	opc					Rn					Rt

No memory ordering (R == 0)

STCLRH <Ws>, [<Xn|SP>]

Equivalent to: LDCLRH <Ws>, WZR, [<Xn|SP>]

Release (R == 1)

STCLRLH <Ws>, [<Xn|SP>]

Equivalent to: LDCLRLH <Ws>, WZR, [<Xn|SP>]

Explanations

<Ws>: Is the 32-bit name of the general-purpose register holding the data value to be operated on with the contents of the memory location, encoded in the "Rs" field.
<Xn|SP>: Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.

Operational Notes

If PSTATE.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored.